<p>Responsibilities:</p> <ul> <li> <p>SOC subsystem architect including documentation of micro-architecture</p> </li><li> <p>Lead design team for major subsystems of large SOCs Qualifications:</p> </li><li> <p>BS/MS degree with 10+ years of relevant work experience</p> </li><li> <p>Expert understanding of digital design and verification practices</p> </li><li> <p>Ability to write RTL based on a specification and simulate vectors to verify RTL</p> </li><li> <p>Experience using System Verilog (SV) and at least two prior RTL designs</p> </li><li> <p>Extensive knowledge of PCIe, USB3, or Power Delivery</p> </li></ul> <p>Experience:</p> <ul> <li>Demonstrate an expert knowledge of System Verilog (SV) or similar verification language </li><li>Demonstrate an expert knowledge of Verilog for chip design and verification </li><li>Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug </li><li>Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.) </li><li>Experience with creating module level test benches and BFMs </li></ul>