<p>Job Details:</p> <p>Job Description:</p> <p>Do Something Wonderful!</p> <p>Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.</p> <p>Want to learn more? Visit our YouTube Channel or the links below!</p> <ul> <li> <p>Life at Intel</p> </li><li> <p>Intel Global Diversity and Inclusion</p> </li></ul> <p>Responsibilities include, but are not limited to:</p> <ul> <li> <p>Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).</p> </li><li> <p>Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).</p> </li><li> <p>Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).</p> </li><li> <p>Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.</p> </li><li> <p>Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.</p> </li><li> <p>Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.</p> </li><li> <p>Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.</p> </li><li> <p>Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block.</p> </li><li> <p>Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.</p> </li><li> <p>Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.</p> </li></ul> <p>Qualifications:</p> <p>You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.</p> <p>Minimum Qualifications:</p> <p>Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience</p> <ul> <li>or - </li></ul> <p>Master's degree in the same fields with 2+ years of relevant experience</p> <ul> <li>or - </li></ul> <p>PhD in the same fields with 1+ years of relevant experience</p> <p>Relevant work experience should be of the following:</p> <ul> <li>Experience with DFT Array Test including MBIST or Scan/ATPG or DFT Verification </li></ul> <p>Preferred Qualifications:</p> <ul> <li> <p>Expertise in Tessent DFT tool</p> </li><li> <p>Expertise in Primetime especially in DFT constraints</p> </li><li> <p>Expertise in Quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT</p> </li></ul> <p>Job Type:</p> <p>Experienced Hire</p> <p>Shift:</p> <p>Shift 1 (United States of America)</p> <p>Primary Location:</p> <p>US, California, Santa Clara</p> <p>Additional Locations:</p> <p>US, Oregon, Hillsboro, US, Texas, Austin</p> <p>Business group:</p> <p>At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.</p> <p>Posting Statement:</p> <p>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.</p> <p>Position of Trust</p> <p>N/A</p> <p>Benefits:</p> <p>We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:</p> <p>https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003</p> <p>Annual Salary Range for jobs which could be performed in the US: 121,050.00 USD - 227,620.00 USD</p> <p>The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.</p> <p>Work Model for this Role</p> <p>This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.</p>