<p>Tesla's Silicon Development Group is looking for a Design-for-Test (DFT) Design Verification Engineer to work on custom ASICs. You will drive state of the art in the area of testability and contribute to product coverage and quality by verifying the DFT features pre-silicon and by delivering test content for post-silicon.</p> <ul> <li> <p>Create Verilog/System Verilog/UVM test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST, JTAG, and boundary scan at block and SoC-level</p> </li><li> <p>Verify top-level features such as power-on self-test, clock observation, clock stop and scan dump</p> </li><li> <p>Run DV regressions & analyze coverage, triage & debug failures</p> </li><li> <p>Run gate level simulations</p> </li><li> <p>Work with the RTL designers on identifying design fixes as needed</p> </li><li> <p>Work with test engineers on delivering pre-Si DV testcases for silicon bring up</p> </li><li> <p>Participate in silicon bring up and post silicon ATE correlation</p> </li><li> <p>Knowledge of testability techniques and features (1149.1, 1149.6, 1687, 1500, Scan, Built-in-Self-Test, Loop-Back etc.) covering digital logic domain, embedded memories and PHY/IOs</p> </li><li> <p>JTAG/1500/1687 networks and languages BSDL, ICL and PDL</p> </li><li> <p>Experience in general design verification methodology, regressions, simulation and debug tools</p> </li><li> <p>Expertise in Verilog or System-Verilog</p> </li><li> <p>Working knowledge of scripting languages such as TCL, python (or another scripting language such as Perl)</p> </li><li> <p>Experience in triaging regressions, debugging, and resolving down to RTL or Testbench issues</p> </li><li> <p>Degree in Computer Engineering or Electrical Engineering or equivalent experience with evidence of exceptional abilities in DFT verification</p> </li></ul>