<p>Job#: 3024515</p> <p>Job Description:</p> <p>Title: Senior FPGA/ASIC Design Engineer</p> <p>Position Overview</p> <p>Seeking an experienced Senior FPGA/ASIC Design Engineer to architect and implement high-performance digital systems for next-generation networking and communication solutions. The ideal candidate will have extensive experience in SoC architecture, RTL design, and leading complex chip development projects from concept to silicon.</p> <p>Key Responsibilities</p> <p>Architecture & Design</p> <ul> <li>Architect and implement high-performance FPGA/ASIC solutions for 10G/100G+ networking applications </li><li>Lead SoC architecture definition and top-level integration from initial design through synthesis and timing closure </li><li>Design and implement high-speed data path architectures including encryption/decryption pipelines (AES-256) </li><li>Develop clock domain crossing (CDC) synchronization designs and packet processing modules </li><li>Create and maintain comprehensive ASIC/FPGA design specifications </li></ul> <p>Technical Leadership</p> <ul> <li>Lead digital design teams through complete chip execution lifecycle (inception to tape-out) </li><li>Coordinate with cross-functional teams including DV, analog design, layout, and software teams </li><li>Provide technical mentorship to junior engineers </li><li>Drive design reviews for functionality and timing requirement sign-offs </li><li>Support lab bring-up, debug, and silicon validation activities </li></ul> <p>Implementation & Verification</p> <ul> <li>Design complex digital blocks: packet processing, error correction (FEC, Reed-Solomon, LDPC), encryption cores, packet buffers, memory interfaces to external DDR/LPDDR4 </li><li>Implement IEEE 802.3 compliant designs (10G-KR, 10GiE, GiE PCS cores) </li><li>Develop synthesis constraints and achieve timing closure for complex designs </li><li>Implement DFT methodology and ATPG for production testing </li><li>Conduct FPGA emulation and validation using Xilinx platforms </li></ul> <p>Required Qualifications</p> <p>Education</p> <ul> <li>M.S. in Electrical Engineering, Computer Engineering, or related field </li><li>B.S. in Electrical Engineering or Computer Engineering </li></ul> <p>Experience</p> <ul> <li>10+ years of ASIC/FPGA design experience </li><li>5+ years leading design teams or chip-level projects </li><li>Proven track record of successful tape-outs and silicon bring-up (ASIC/FPGA) </li></ul> <p>Technical Skills</p> <ul> <li>Expert-level proficiency in Verilog/SystemVerilog RTL design </li><li>Strong experience with Xilinx FPGA platforms (Versal, Kintex, Virtex series) </li><li>Deep understanding of high-speed networking protocols (Ethernet, PCI-Express, USB) </li><li>Expertise in synthesis, static timing analysis, and timing closure (Synopsys/Cadence tools) </li><li>Experience with forward error correction algorithms and encryption standards (AES, DES) </li><li>Proficiency with scripting languages (Python, Perl) for design automation </li><li>Hands-on experience with FPGA tools: Vivado, Vitis, Chipscope, ILA </li></ul> <p>Preferred Qualifications</p> <ul> <li>Mixed-signal design and verification experience (cocotb, UVM) </li><li>Experience with analog interfaces and power management designs </li><li>Knowledge of USB Type-C, USB PD, and power delivery protocols </li><li>Familiarity with formal verification methodologies </li><li>Patent portfolio in digital design or error correction </li><li>Experience with satellite communication systems or aerospace applications </li></ul> <p>Key Competencies</p> <ul> <li>Strong problem-solving skills with ability to debug complex system-level issues </li><li>Excellent communication skills across technical and non-technical audiences </li><li>Self-motivated with ability to work independently and drive projects to completion </li><li>Detail-oriented with focus on design quality and meeting schedules </li><li>Proven ability to innovate and adopt cutting-edge techniques from research </li></ul> <p>Tools & Technologies</p> <ul> <li>FPGA: Xilinx Versal, Kintex, Virtex, Spartan families </li><li>EDA Tools: Cadence, Synopsys </li><li>Languages: Verilog, SystemVerilog, Python, Perl, C/C++, MATLAB </li><li>Protocols: Ethernet (10G/25G/100G), PCI-Express, SERDES, LVDS </li><li>Version Control: Git, Jira, Confluence </li><li>Test Equipment: IXIA, XENA </li></ul> <p>Apex Systems is a world-class IT services company that serves thousands of clients across the globe. When you join Apex, you become part of a team that values innovation, collaboration, and continuous learning. We offer quality career resources, training, certifications, development opportunities, and a comprehensive benefits package. Our commitment to excellence is reflected in many awards, including ClearlyRated's Best of Staffing in Talent Satisfaction in the United States and Great Place to Work in the United Kingdom and Mexico. Apex uses a virtual recruiter as part of the application process. Click here for more details.</p> <p>Apex Benefits Overview: Apex offers a range of supplemental benefits, including medical, dental, vision, life, disability, and other insurance plans that offer an optional layer of financial protection. We offer an ESPP (employee stock purchase program) and a 401K program which allows you to contribute typically within 30 days of starting, with a company match after 12 months of tenure. Apex also offers a HSA (Health Savings Account on the HDHP plan), a SupportLinc Employee Assistance Program (EAP) with up to 8 free counseling sessions, a corporate discount savings program and other discounts. In terms of professional development, Apex hosts an on-demand training program, provides access to certification prep and a library of technical and leadership courses/books/seminars once you have 6+ months of tenure, and certification discounts and other perks to associations that include CompTIA and IIBA. Apex has a dedicated customer service team for our Consultants that can address questions around benefits and other resources, as well as a certified Career Coach. You can access a full list of our benefits, programs, support teams and resources within our 'Welcome Packet' as well, which an Apex team member can provide.</p> <p>Employee Type:</p> <p>Contract</p> <p>Location:</p> <p>Los Angeles, CA, US</p> <p>Job Type:</p> <p>Engineering and Technicians</p> <p>Date Posted:</p> <p>March 4, 2026</p> <p>Pay Range:</p> <p>$108 - $108 per hour</p> <p>Similar Jobs</p> <ul> <li>Engineering - Engineer Digital 3 </li><li>FPGA Engineer - P4- Cleared On-Site </li><li>FPGA Engineer - P2 - Cleared On-Site </li><li>FPGA Engineer - P3 - Cleared On-Site </li><li>Digital Design Engineer - P3- Cleared On-Site </li></ul>