<p>Meta is hiring ASIC Implementation Engineers within our Infrastructure organization.</p> <p>Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing Experience with SOC CDC signoff Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other Hardware Description Language Experience with communicating across functional internal teams and vendors Scripting and programming experience using Perl/Python, TCL, and Make Experience with SOC Design Integration and Front-End Implementation Knowledge of Timing/physical libraries, SRAM Memories Experience with Netlist CDC Analysis and improving Mean Time Between Failures Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Experience with developing structural rule based checks for RTL & Netlist</p> <p>Responsibilities: Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and Firmware teams and develop reset groups and the corresponding reset sequence for RDC Perform RTL Lint and work with the Designers to create waivers Perform RTL Design for Testability Analysis and improve the Design for Testability coverage for Stuck-at faults Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all Front-end tools including (Lint, CDC, RDC,) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback</p>